A 40-Gb/s Wireline Backplane Receiver in 65-nm CMOS Technology
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === In this thesis, a 40-Gb/s receiver has been implemented in 65-nm CMOS technology, which composed of three critical components of a wireline backplane receiver – an analog equalizer, a clock and data recovery circuit (CDR), and a demultiplexer (DMUX). The analog...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83437373053440643737 |