Plasma Process Induced Damage Effect on Low Temperature Poly-Silicon Thin Film Transistors

• Main Authors: Chang, Jiun-Jye, 張鈞傑
• Other Authors: Chang-Liao, Kuei-Shu
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/66165290933503552864

博士 === 國立清華大學 === 工程與系統科學系 === 101 === Low temperature polycrystalline silicon (LTPS) technology is the most promising technology to manufacture high performing thin film transistors (TFTs). LTPS TFT with high mobility can reduce device size more than the conventional amorphous silicon TFT. To achieve high resolution and good process repetitiousness, plasma dry etch processes were wisely adopted in LTPS TFT manufacturing. In this thesis, we extensively studied the plasma process induced damage (PPID) effects and evaluated various processes in order to recover and against plasma process induced damage in LTPS TFT fabrication. At first, the device characteristics and degradation of LTPS TFT in poly-Si plasma process were investigated. Different channel widths and lengths were designed to discuss the PPID effects of poly-Si etch process. Device reliability was also studied by electrical stressed, such as hot carrier stressing, to reveal the damage effects. In the meanwhile PPID recovery of LTPS TFT in poly-Si plasma process was also investigated. Thermal anneal processes with different ambient and post-etched plasma treatments were carried out to recover the damage effects by PPID. Furthermore, post-etch treatments with plasma in hydrogen ambient and laser anneal have been demonstrated to significantly remove PPID effects. It is believed that the deep trapping states can be repaired by hydrogen species, and the damaged channel edge of the active region are re-crystallized by laser anneal, respectively. In the second part, the metal gate plasma process on the electrical characteristics and degradation of LTPS TFT were investigated. Different channel widths and lengths were designed to discuss the PPID effects of metal gate etch process. Devices with thick metal gates have worse electrical reliability after PBTI tested due to plasma process induced latent damage. Dual gate TFT is adopted to suppress leakage current by reducing the electric field from gate to source/drain. The reliability of dual gates TFT is degraded due to serious PPID effects, particularly for device with thick metal gate. Dual gates devices incur serious plasma damage due to twice as many exposed channel edges as single gate devices in the metal gate etch process. Reliability and trap density were also studied by electrical stressing, such as high filed gate voltage stressing, to reveal the damage effects. In the meantime, PPID recovery of LTPS TFT in metal gate plasma process was studied. Thermal anneal process with different ambient and post-etched plasma treatment were carried out to recover the damage effects. It is demonstrated that the post-etch treatments with thermal annealing and plasma in NH3 ambient can recover PPID because hydrogen species can repair the trapping states. Gate dielectric with thin silicon nitride stacked upon silicon oxide was adopted to resist PPID. Furthermore, the electrical characteristics of LTPS TFT show significantly improvement by post-etch NH3 treatment on thin silicon nitride stacked with silicon oxide. In addition, we have also studied antenna effects of LTPS TFT during metal gate plasma etch process. Devices with a high antenna ratio, and especially those that undergo thick metal patterning, exhibit obvious degradation and poor reliability when stressed. These results are concluded to be caused by damage to the gate oxide. Such devices will exhibit huge damage and consequent degradation upon electrical stressing. Unfortunately, such damaged devices cannot be easily recovered by thermal or hydrogenation treatment.