| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 101 === Network-on-Chip (NoC) has become an essential interconnect technology for many-core systems because of its scalable and flexible infrastructure. However, the router-based NoC structure has long latency (large hops) between connected cores. Also, large power consumption is spent on
routers and FIFOs. To address the later issue (for lower power), a Dynamic Voltage and Frequency Fcaling (DVFS) scheme is proposed for traditional NoC.
In this thesis, we first designed a low-cost low-latency synchronous FIFO to support DVFS in NoC. Then, in order to better understand the impact of latency introduced by NoC (and DVFS at lower frequency), we proposed a quick timing
simulator for DVFS NoC.
The simulator can take several important factors of a NoC into account: worm-hole switching, inter-traffic relations and speed difference between FIFOs.
In the experiment, the proposed simulator can correctly calculate all timings with a speedup up to 95 times as
compared with a cycle-accurate model.
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