Timing Simulation for Network-on-Chip with Dynamic Frequency Scaling
碩士 === 國立清華大學 === 電機工程學系 === 101 === Network-on-Chip (NoC) has become an essential interconnect technology for many-core systems because of its scalable and flexible infrastructure. However, the router-based NoC structure has long latency (large hops) between connected cores. Also, large power consum...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/49388785915860496190 |