Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture
碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === Current trends in processor design have migrated toward chip multiprocessors (CMPs). CMPs are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processors. However, the conventio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64535275185786278655 |