Design of Null Convetion Logic (NCL) Pipelines with Power Gating
碩士 === 國立彰化師範大學 === 電子工程學系 === 101 === Abstract As the feature size continues to shrink and the corresponding transistor density increases, power dissipation has become an important concern in nanoscale CMOS VLSI design. Power gating is one of the most effective techniques for leakage reduction. On...
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ndltd-TW-101NCUE54280062015-10-13T22:12:40Z http://ndltd.ncl.edu.tw/handle/91419208309610888204 Design of Null Convetion Logic (NCL) Pipelines with Power Gating 具電源閘控機制的零協議邏輯 (NCL)管線電路之設計 Ming-Hsun Hsieh 謝明勳 碩士 國立彰化師範大學 電子工程學系 101 Abstract As the feature size continues to shrink and the corresponding transistor density increases, power dissipation has become an important concern in nanoscale CMOS VLSI design. Power gating is one of the most effective techniques for leakage reduction. On the other hand, Asynchronous circuits are data-driven and active only when performing useful work. That is, asynchronous circuits do not switch when inactive and inherently have the advantage of offering the equivalent of fine-grain clock gating. This thesis proposed three novel fine-grain power-gating asynchronous pipelines, called PG-MTNCL, PG-MTNCL-ES, and PG-MTNCL-ES-EC, respectively, which combine the advantage of power gating techniques and asynchronous circuits. Power gating can be implemented in the fine-grain or coarse-grain manner. The fine-grain power gating approach has more opportunities to reduce leakage at run-time than the coarse-grain power gating approach. When the logic blocks in the proposed fine-grain power-gating pipelines have no valid inputs, they enter the sleep mode immediately to reduce leakage power dissipation. Moreover, two techniques, early sleep and early completion, have been developed for the fine-grain power-gating pipelines to further reduce leakage dissipation and operation latency. In this thesis, we employed those fine-grain power-gating pipelines to implement the 8-bit five-stage pipelined Kogge-Stone adder in order to evaluate their effectiveness for low-power design. Also, we have compared the performance of the proposed three fine-grain power-gating pipelines with that of three traditional NCL pipelines, Basic-NCL, NCL-EC, and MTNCL-EC. Keywords: Asynchronous circuits, NCL (Null Convention Logic), Power Gating, Static Power Dissipation Meng-Chou Chang 張孟洲 2013 學位論文 ; thesis 119 zh-TW |
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碩士 === 國立彰化師範大學 === 電子工程學系 === 101 === Abstract
As the feature size continues to shrink and the corresponding transistor density increases, power dissipation has become an important concern in nanoscale CMOS VLSI design. Power gating is one of the most effective techniques for leakage reduction. On the other hand, Asynchronous circuits are data-driven and active only when performing useful work. That is, asynchronous circuits do not switch when inactive and inherently have the advantage of offering the equivalent of fine-grain clock gating.
This thesis proposed three novel fine-grain power-gating asynchronous pipelines, called PG-MTNCL, PG-MTNCL-ES, and PG-MTNCL-ES-EC, respectively, which combine the advantage of power gating techniques and asynchronous circuits.
Power gating can be implemented in the fine-grain or coarse-grain manner. The fine-grain power gating approach has more opportunities to reduce leakage at run-time than the coarse-grain power gating approach. When the logic blocks in the proposed fine-grain power-gating pipelines have no valid inputs, they enter the sleep mode immediately to reduce leakage power dissipation. Moreover, two techniques, early sleep and early completion, have been developed for the fine-grain power-gating pipelines to further reduce leakage dissipation and operation latency.
In this thesis, we employed those fine-grain power-gating pipelines to implement the 8-bit five-stage pipelined Kogge-Stone adder in order to evaluate their effectiveness for low-power design. Also, we have compared the performance of the proposed three fine-grain power-gating pipelines with that of three traditional NCL pipelines, Basic-NCL, NCL-EC, and MTNCL-EC.
Keywords: Asynchronous circuits, NCL (Null Convention Logic), Power Gating, Static Power Dissipation
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Meng-Chou Chang |
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Meng-Chou Chang Ming-Hsun Hsieh 謝明勳 |
author |
Ming-Hsun Hsieh 謝明勳 |
spellingShingle |
Ming-Hsun Hsieh 謝明勳 Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
author_sort |
Ming-Hsun Hsieh |
title |
Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
title_short |
Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
title_full |
Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
title_fullStr |
Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
title_full_unstemmed |
Design of Null Convetion Logic (NCL) Pipelines with Power Gating |
title_sort |
design of null convetion logic (ncl) pipelines with power gating |
publishDate |
2013 |
url |
http://ndltd.ncl.edu.tw/handle/91419208309610888204 |
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