| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 101 === Both the C-band and V-band fully integrated silicon-based power amplifiers are designed in the thesis, using 0.18 m and 90 nm CMOS processes by tsmcTM, respectively. In the first part, reactance compensation network is adopted for the circuit design for wideband consideration; a 5-6 GHz class-E high efficiency power amplifier was implemented. In the second part, a high gain and wideband V-band power amplifier was implemented by adopting wideband matching network technique.
Measurement results are summarized below: The 5-6 GHz class-E power amplifier fabricated in 0.18 m CMOS technology achieves a power gain of 5.45 dB, a saturation output power of 22.79 dBm, and a power-added-efficiency of 19.71%. The V-band power amplifier with high gain and wide-band in 90 nm CMOS Technology achieves a power gain of 21.8 dB, an output power at 1-dB gain compression point of 8.1 dBm, a saturation output power of 12.75 dBm, and a power-added-efficiency of 10.75%.
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