| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 101 === Aging and interconnect as well as soft errors have become the three most critical reliability issues for nano-scaled CMOS designs. In this work, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, interconnect issue is also considered for soft errors in circuits at 90-nm technology and below. In the end, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models or the wire models. As the result of aging-aware part, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (~19%) and thus needs to be considered, simultaneously, during circuit analysis. On the other hand, the capacitance of wire amplifies soft error rate, so interconnect issue also should be concerned. Experimental result shows that our SSER framework not only considering capacitance of wire but also considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.
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