A Parallel Layer-Aware Partitioning Algorithm for TSV Minimization in 3D ICs
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === As compared to the traditional two-dimensional (2D) ICs, 3D integration is considered as a breakthrough technology which has the potential to provide significant performance and functional benefits. This emerging technology enables stacking multiple layers...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18320803350068987513 |