High-Level Synthesis on Various Distributed Register Architectures
博士 === 國立交通大學 === 電子研究所 === 101 === In deep submicron era, the wire delay is no longer negligible and is becoming a dominant factor of system performance. Distributed register (DR) based architectures, which try to keep most interconnects local within a cluster and thus minimize the number of long i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/xvk8sq |