Nanoepitaxy of III–V epi–layer onto nanopatterned and nanoscale stripe patterned Si substrate

• Main Authors: Chao-WeiHsu, 許晁瑋
• Other Authors: Yan-Kuin Su
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/39654694959280214262

博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 101 === GaAs and InAs are grown on geometric nanopatterned and nanoscale stripe patterned Si substrates with SiO2 as a mask by metal–organic vapor–phase epitaxy. Theoretical models suggest the possibility of strain relief and dislocation reduction via a decrease in the initial epitaxial areas to the nanoscale regime. Threading dislocations, which are stacked on the lowest–energy facet plane, are trapped by the SiO2 patterns, reducing the number of dislocations. For GaAs on a 55–nm round–hole patterned Si substrate with SiO2 as a mask, the etching pit density of the GaAs surface is about 3.3 × 10^5 cm^-2. Compared with the full width at half maximum measurement (FWHM) from X–ray diffraction (XRD) ω/2θ scans patterns and photoluminescence spectra of GaAs on a planar Si (001) substrate, those of GaAs on the 55–nm round–hole patterned Si substrate are reduced by 39.6 % and 31.4 %, respectively. The use of 70–nm–wide SiO2 convex–top patterns can suppress the coalescence dislocations of the epi–layer and lead to a further decrease the FWHM values of the XRD ω/2θ scan patterns by 11.5 % compared to those obtained with 70–nm–wide rectangular–top SiO2 patterns. Compared with the conventional planar Si substrate, depositing the epi–layers onto nanoscale stripe patterned Si substrates decreases the dislocation density from about 109 cm-2 to almost zero. With the aspect ratio increased from 0.44 to 2.04, the etching defect pit density can be significantly decreased. Almost etching–pit–free surfaces of GaAs and InAs nanofins are achieved using nanoscale stripe patterned Si (001). The lattice constants measured from the GaAs and InAs nanofins are 5.63 Å and 6.04 Å, respectively, which are similar to those of natural GaAs and InAs. An ultraviolet metal–semiconductor–metal photodetector was prepared on an almost crack–free epi–layer surface. With a 5–V applied bias, the UV–to–visible rejection ratio was estimated to be 1479 and the measured leakage current was 1.5×10^-11 A.