| Summary: | 碩士 === 國立成功大學 === 材料科學及工程學系碩博士班 === 101 === Chemical mechanical polishing (CMP) has been recognized as the most effective planarization technology in wafer processing, and its plays an important role in the state of the arts integrated circuits (IC) fabrication. For CMP, the polishing uniformity of entire wafer as well as the possible dishing and erosion observed in interconnects are the most critical concerns and therefore various analytical and numerical investigations have been conducted for enhancing CMP performance. However, due to its multi-disciplinary nature, it is difficult to conduct a full scale analysis. In particular, finite element analysis (FEA) has been widely used in associated with polishing model such as Preston’s equation for predicting the mechanical stressing effect in CMP. However, in the past, due to lack of efficient geometry updating capability, FEA can only use the initial geometry for simulation, which cannot count the geometry evolution and could possibly results in error. For this reason, in this thesis, a novel chemical-mechanical polishing modeling schemes for addressing the mechanical aspect in both wafer and device levels is analyzed and realized. The method integrates finite element analysis with Matlab for controlling the simulation geometry. The method begins with a CMP finite element model and, the stress of a particular step can be determined and the corresponding MRR can be calculated by FEA. Consequently, the surface topology is then updated based on the calculated MRR distribution, using Matlab and is used for FEA at next time increment. The interaction continues until the entire process is finished. Both wafer and device level simulations are performed by the proposed method. In wafer level, it is observed that the discrepancy between the proposed method and the traditional FEA based on initial geometry is not significant for high uniformity variation tolerance. However, as the tolerance reduceds to within 10 nm, the difference in uniformity prediction becomes remarkable. On the other hand, for device level, the proposed method can successfully predict dishing and erosion phenomena and the simulation results agree with those experimental data reported in previous literatures. Finally, essential parametric studies are performed for systematically investigating various processing parameters such as pad modulus and selectivity as demonstrations for addressing the structural integrity of interconnected structures after polishing and for the possible applicability of using the proposed method for guiding future CMP process optimization.
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