Study on the Recovery Effect and Instability of Threshold Voltage of Amorphous Silicon TFTs under DC/AC Stresses

• Main Authors: Yeo-Ming Chi, 紀佑旻
• Other Authors: Han-Wen Liu
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/xvzskm

碩士 === 國立中興大學 === 光電工程研究所 === 101 === Amorphous silicon thin film transistors, although the carrier mobility and device stability were not as good as poly-Si thin film transistors, due to the development of longer maturity of the technology and the low cost, therewas still valuable exploration on the stability of these devices in the driving circuits. In this study, the symmetrical structures of amorphous silicon thin film transistors were used. For direct current (DC) biased stress, when we applied a DC gate voltage stress, the insulating layer (SiNx) and channel layer would be subject to the carrier trapping and the defect states creation mechanisms, so that the threshold voltage was changed. If we provided a positive biased stress on the gate, the electrons in the channel layer were attracted by the positive voltage, and the major trapping carriers would be electrons. If we gave a negative biased stress, the main carriers would be holes, resulting in hole trapping mechanism. No matter what negative or positive biased stresses on the gate, the defect creation mechanism would always make the threshold voltage increase. When the carriers transported, some of the carriers would be trapped in the insulating and channel layers. Although few carriers might enter the insulating and the channel layers, but not trapped, they would be influenced by the trapped carriers with the same polar charge and backed to drain and source. This effect was called recovery effect. The mobility of a-Si TFTs was much smaller than that of polySi ones, therefore, it was more easy to observe this recovery effect in the stability test of a-Si TFTs. If the threshold voltage became smaller after recovering, it represented the electron trapping was the dominant degradation mechanism.. If the threshold voltage increased after recovering, it represented the hole trapping was the dominant degradation mechanism. For the alternating current (AC) biased stress, we applied to the biased stress on the gate and changed the frequency of these AC signals. In the condition of the positive biased stress, regardless of the AC signals frequencies, the Vth instability of a-Si TFTs was not dependent on these frequencies, because the major degradation in the device was caused by electron trapping mechanism. The accumulating speed of electrons would be much faster than that of the applied AC signal, and therefore, the degradation was not subject to the changing of AC frequency. On the contrary, in the negative biased stress condition, the threshold voltage shift was significantly affected by the changing of AC frequency, resulting from the high resistivity between the junctions of the accumulating hole and n+-a-Si(i.e. source and drain) layers. When the pulse signals of negative gate voltage changed rapidly, there was a RC delay effect existing in hole trapping mechanism. When we fixed the signal amplitude of 39 V and a frequency of 10 Hz, and changed the lowest value of the biased pulse signals, the balanced point of the Vth degradation almost achieved for the condition of pulse signal in the range of -10~29 V, and the final increase of Vth is caused by the defect states creation mechanism.