Temperature and CHC Stress for Nano-regime Si-capped Layer (110) pMOSFETs with Strained CESL Processes
碩士 === 明新科技大學 === 電子工程研究所 === 101 === With the advanced process technology entering the nano-scale era, the semiconductor industry due to the feature-size shrinkage of semiconductor devices faces several strict challenges, such as a thin gate oxide layer causing carrier direct tunneling and the gate...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/28999013427120722743 |