Nanometer Processes in Strain Engineering Characteristics of FinFET Devices and Low Noise Amplifier Circuit Design

• Main Authors: Wei-yen Peng, 彭偉晏
• Other Authors: Hsin-CHia Yang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/98590649290895145317

碩士 === 明新科技大學 === 電子工程研究所 === 101 === As the semiconductor devices shrink to down below nanometer-scale, the obvious benefits lie on the low-cost fabrication and ultra-high speed. Nevertheless, the serious requirements are the must. Unfortunately, the shrunk traditional CMOSFET devices no longer satisfy the requirements achieving the characteristics that Integrated Circuits demand. One of the solutions is the use of strain engineering. There are two kinds of straining techniques being used; one is uni-axial straining type and the other is bi-axial straining one. In this study, <100> wafers are used for the straining techniques. In addition to the global strain, an epi-SiGe layer is deposited on Si substrate as a cap layer. The contact etch stop layer (CESL) process was applied on the gate electrodes to form the tensile/compressive strain. The local strain engineering enhances the carrier mobility of nMOSFET devices and thus increases the driven current as well. Fin-FET transistors are used for controlling circuits with Source/Drain and Gate looking like fork-like shaped structure. Furthermore, the single FinFET device has 3D fin-like channel with gate poly crossing over. As the size shrinks, the absence of substrate make the FinFET devices much less leaky and therefore Gate can easily take control of the expected functions. In a word, the designs of 3-D transistors tremendously improve the controllability of the circuit and reduce its leakage current compared to the traditional CMOSFET devices. One will study single-channel and eleven-channel devices and how they can be affected referring to different ion implantation energy (20eV，15eV). Low Noise Amplifiers (LNA) predominate the receiver as a pre-amplifier with the function of suppressing the generated noises in the whole system. This component must totally control its own generated noise and thus enjoy the leading role reducing the negative effects coming from any possible disturbances of noises. One uses TSMC 90nm CMOS process implemented in the Advanced Design System (ADS, by Agilent) to design the circuit, in which LC tank and LC in series take the role choosing the central working frequencies. In this study, much higher radio frequencies are taken into account. Passive devices again are used for the impedance matching. S11 and S2 show the appropriate matching causing the high gain S21. Isolations are found to be good. NF’s are higher than the ones at lower working frequencies but acceptable. All the above prove the availability of RFIC in the promising expectation. I believe great reference value of this test for the future development of the communications circuits.