Low Power Gated Clock Tree Construction Algorithm for Manufacturing Processes
碩士 === 中原大學 === 資訊工程研究所 === 101 === Through the advance of IC design, how to minimize the power consumption has become a very important issue. Clock gating technique has been used widely in high performance VLSI design to reduce clock network power consumption. We can reduce power consumption by shu...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/49265862503157815933 |