Study of Nano-CMOS All-Digital Delay-Locked Loops
碩士 === 國立中正大學 === 電機工程研究所 === 101 === This paper presents the design of a wider operation range ADDLL for clock synchronization in a SoC. Cyclic-HDSC DLL is adopted to achieve low power, high resolution, low output jitter and can operate at wide operating frequency ranges. Cyclic-coarse-fine synchro...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39889797420425045440 |