Standard-cell-like Via-configurable Structured ASIC for Mask Cost Reduction
博士 === 元智大學 === 資訊工程學系 === 100 === As process technology moves to more advanced nodes, forming regular layouts on some critical layers becomes indispensable to mask tooling cost reduction and high-yield manufacturing of integrated circuits. Design technologies employ pre-fabricated/predefined regula...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/54092264999732205692 |
| Summary: | 博士 === 元智大學 === 資訊工程學系 === 100 === As process technology moves to more advanced nodes, forming regular layouts on some critical layers becomes indispensable to mask tooling cost reduction and high-yield manufacturing of integrated circuits. Design technologies employ pre-fabricated/predefined regular layout structures are hence considered as a viable solution to achieving high-yield production with low mask tooling cost. A structured ASIC with prefabricated yet configurable logic block arrays and possibly some predefined routing fabrics is one of technology choices that have these characteristics. In this dissertation, we study the problem of designing via-configurable logic blocks (VCLB) for structured ASIC. A VCLB can be used physically to build regular logic arrays and logically to implement various logic functions. First, we investigate some important VCLB design issues. We particularly focus on exploring VCLB granularity for area optimization and creating VCLB layouts that enable a standard-cell-like design style for leveraging industrial standard cell design tools. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic gate. We devise five new VCLBs and construct several cell libraries based on these VCLBs. The experimental results show that a medium-grained VCLB that realizes a rich set of logic functions attains the best performance. In the later part of the dissertation, we propose a systematic way to study the granularity problem furthermore. We devise six new VCLBs and construct several cell libraries based on these VCLBs. These VCLBs have their poly wires uniformly and regularly laid out on the substrate in terms of a certain pitch. Our experimental results show that a VCLB with four transistor pairs laid above a single non-segmented diffusion attains the smallest area and good timing performance.
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