Pico-Second Level Vernier Delay Line for Register Metastability Measurements Technique and Chip Design

• Main Authors: Shao-hsuan Wang, 王少軒
• Other Authors: Po-Hui Yang
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/26407190975022909650

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 100 === In current system on a chip (SoC), the asynchrony between digital signals and transmitting process of the system circuit often causes insufficient signal setup time or hold time, which in term leads to metastable state and finally causes logic error. In metastable state, the time between each logic signals is only several pico-seconds, which makes it difficult to capture the metastable state or even to analyze it. Several measuring circuits have been proposed by previous studies to solve the aforementioned problem. Though these circuits can reach the pico-second level, they are hard to control and difficult to be designed and realized. This thesis proposed a measuring technique based on vernier circuit, which is not only stable but can easily produce two logic signals with only pico-second-level delay time. This thesis applied feedback type D latches and D flip-flops as the measurement basis. When applied a CMOS 0.18um process to simulate our idea, the timing discrepancy of metastable state between a D latch and a D flip-flop was about 80ps-302ps. In this thesis, the simulation produced a measuring circuit with a 10ps timing difference. Under proper sizing, the timing difference of the same circuit can be produced ranging from zero to 320ps. The study also successfully simulated the metastable state of a D latch at 120ps in 10ps timing resolution. Moreover, the chip of the measuring circuit was also successfully simulated; whose simulated result was the same before and after layout.