Pico-Second Level Vernier Delay Line for Register Metastability Measurements Technique and Chip Design
碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 100 === In current system on a chip (SoC), the asynchrony between digital signals and transmitting process of the system circuit often causes insufficient signal setup time or hold time, which in term leads to metastable state and finally causes logic error. In...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26407190975022909650 |