The Reliability of a-Si:H TFTs at Various Temperatures and Gate/Drain Biases

• Main Authors: Zen-Fan Huang, 黃任範
• Other Authors: 黃恆盛
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/b9ap95

碩士 === 國立臺北科技大學 === 機電整合研究所 === 100 === The hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been widely studied. For the reliability, it still has space to explore especially in high temperature. For various gate/drain biases, the degradation mechanisms of the TFT are not clear, and no suitable model exists. That is the motivation of this study. In this study, the tested TFTs are inverted staggered type and fabricated in Giantplus Technology Corporation. The reliability tests are executed with constant voltage stress (CVS) by various gate/drain biases at temperatures of 25, 75, and 125℃.We also measure the TFT characteristics and investigate the degradation mechanisms in gate insulator and channel interface. To simulate the real operation of the TFTs, the tests in AC condition is also performed. From the experimental results, the degradation becomes more serious under high gate stress voltage and temperature. When the drain stress voltage increases, the degradation decreases slightly. We infer that the electric field near the drain decreased the effect of the gate voltage stress, it likes to set a stress of negative gate bias. The threshold voltage shift and drain current degradation decreased with increasing drain stress voltages. For applied operation voltage to the gate and VD=0 stress at 125℃, the Ion degradation is obviously (about 70%). The ΔVt decreases from 8 V to 6V and ΔS decreases to 0.15V/dec with increasing the drain stress voltage.　For the AC gate bias stress, the degradations are more serious with higher frequency and duty ratio. It might be the carriers have no enough time to de-trapped from the gate insulator and degrade more seriously with increasing carriers.