Reliability Consideration with Rectangle - and Double - Signal Through Silicon Vias Insertion for 3D Thermal-Aware Floorplanning

• Main Authors: Chih-han Hsu, 許智涵
• Other Authors: Shanq-Jang Ruan
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/56730754121679659792

碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also occur unexpected performance loss. In this thesis, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability is. However, it also implies a larger area. Therefore, we develop a methodology to manipulate thermal-aware floorplan with the tradeoff among the number of STSVs, reliability, and area of a chip. Moreover, we manage our manipulated floorplan with precise thermal model for TTSVs insertion at via channel. Experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, thereby improving reliability. Furthermore, temperature can be maintained around 80℃ with minimal TTSVs after inserting TTSVs.