Improving Simulation-Based and Formal Verification Techniques by Automatic High-Level Design Intent and Invariant Extractions
博士 === 國立臺灣大學 === 電機工程學研究所 === 100 === In the dissertation, we build an open source RTL framework, QuteRTL, which can serves as a front-end for the researches in RTL synthesis and verification. Users can use our framework to read in RTL Verilog designs, obtain CDFGs, extract high-level design inform...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20419467411383504170 |