Self-Heating-Aware Buffered Clock Tree Synthesis
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Temperature affects clock signal delays. Without considering temperature effects, clock skew could be significantly increased and chip performance might be accordingly degraded. Most existing temperature-aware clock tree synthesis methods have two major drawbac...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55363415241953370857 |