A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan

碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equatio...

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Bibliographic Details
Main Authors:	Yu-Chiuan Huang, 黃鈺筌
Other Authors:	Chien-Mo Li
Format:	Others
Language:	en_US
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/75226996277198117129

id	ndltd-TW-100NTU05428002
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spelling	ndltd-TW-100NTU054280022015-10-16T04:02:51Z http://ndltd.ncl.edu.tw/handle/75226996277198117129 A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan 用於減輕掃描鍊位移時電壓降峰值的測試時域最佳化之平行化模擬技術 Yu-Chiuan Huang 黃鈺筌碩士國立臺灣大學電子工程學研究所 100 Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equations. This thesis presents a new TCDO algorithm that directly changes flip-flops where peak IR drop occurs. A massive parallel algorithm using graphic processor unit (GPU) is adopted to speed up the IR-drop calculation during optimization. The experimental data on large benchmark circuits show that peak IR drop values are reduced by 49% on the average compared with circuits before optimization. Our proposed technique quickly optimizes a half million gate design within 2 hours. Chien-Mo Li 李建模 2011 學位論文 ; thesis 65 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equations. This thesis presents a new TCDO algorithm that directly changes flip-flops where peak IR drop occurs. A massive parallel algorithm using graphic processor unit (GPU) is adopted to speed up the IR-drop calculation during optimization. The experimental data on large benchmark circuits show that peak IR drop values are reduced by 49% on the average compared with circuits before optimization. Our proposed technique quickly optimizes a half million gate design within 2 hours.
author2	Chien-Mo Li
author_facet	Chien-Mo Li Yu-Chiuan Huang 黃鈺筌
author	Yu-Chiuan Huang 黃鈺筌
spellingShingle	Yu-Chiuan Huang 黃鈺筌 A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
author_sort	Yu-Chiuan Huang
title	A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
title_short	A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
title_full	A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
title_fullStr	A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
title_full_unstemmed	A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
title_sort	parallel simulation technique for test clock domain optimization to reduce peak ir drop during scan
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/75226996277198117129
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A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan

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