A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equatio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75226996277198117129 |