Design and Implementation of Low Thermal Drift and Low-Noise Capacitive Multi-Channel Sensing Interface CMOS-MEMS Accelerometers

• Main Authors: Liu, Yu-Chia, 劉育嘉
• Other Authors: Fang, Weileun
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/83365996554147688064

博士 === 國立清華大學 === 奈米工程與微系統研究所 === 100 === There are many different fabrication processes for Micro-Electro-Mechanical System (MEMS). However, the standard fabrication process is a major factor which plays an important role in MEMS. In this study, a capacitive sensing chip is proposed to use TSMC 0.35 μm 2-polysilicon 4-Metal (2P4M) standard process. Two novel designs together with capacitive interface circuitry of accelerometers were respectively proposed in thesis. First study presents a simple approach to improve the performance of CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature; and the thickness of metal layer can be easily adjusted by process. Thus, the performance of capacitive accelerometer (i.e., structure deformation, sensitivity) can be improved significantly. Second study proposed the stacking of pure oxide layers as the mechanical structures for CMOS-MEMS accelerometer has been developed and demonstrated for the first time. Thus, the distribution of metal-oxide composites in CMOS-MEMS accelerometer is changed from area to line. Such design has the following advantages to solve the initial deformation of suspended MEMS structures due to the residual stresses of metal-oxide films, as well as the thermal deformation of suspended MEMS structures due to the thermal expansion coefficient (CTE) mismatch of metal-oxide films. The parasitic capacitance of sensing electrodes routing underneath the proof-mass also can be further reduced. In addition, the CMOS multi-channel readout circuit on a single chip was developed to sense the time-varient sensing signal. Thus, the smallest footprint of chip size can be achieved.