A Column-Parallel 10-bit SAR ADC with Linearity Calibration for CMOS Image Sensor

• Main Authors: Tsai, Shan-Ju, 蔡尚儒
• Other Authors: Hsieh, Chih-Cheng
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/72207044819455496773

碩士 === 國立清華大學 === 電機工程學系 === 100 === This thesis presents a column-parallel analog-to-digital converter (ADC) with linearity calibration for CMOS image sensor. The architecture of the ADC is successive approximation ADC (SA ADC), which is a suitable architecture for low power consumption applications. A multi-segmented capacitive digital-to-analog converter is utilized to reduce both area and the power consumption of the DAC. A new calibration methodology is proposed to eliminate the linearity problem resulting from the segmented DAC. Adaptive reset configuration (ARC) calibration methodology is proposed in this thesis. ARC eliminates the non-linear part of the transfer curve by setting different switch configuration during the reset cycle of the DAC according to different reference voltage acquired from the conversion. A prototype experimental chip is fabricated by 0.18um mixed signal CMOS process. According to the measurement result, the differential non-linearity is reduced from +8.56 / -0.43 LSB to +1.67 / -1 LSB, and the integrated non-linearity is improved from +6.39 / -6.77 LSB to +3.31 / -4.36. The prototype ADC consumes 19.7uA, 35.46uW at 1.8V voltage supply. Some unexpected non-linearity was found, and the solutions are also discussed in this thesis.