A Column-Parallel 10-bit SAR ADC with Linearity Calibration for CMOS Image Sensor
碩士 === 國立清華大學 === 電機工程學系 === 100 === This thesis presents a column-parallel analog-to-digital converter (ADC) with linearity calibration for CMOS image sensor. The architecture of the ADC is successive approximation ADC (SA ADC), which is a suitable architecture for low power consumption application...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72207044819455496773 |