| Summary: | 碩士 === 國立清華大學 === 光電工程研究所 === 100 === As the transistors enters the scales of the nanometer regime, metallic interconnect will be highly inefficient in several issues, such as poor scalability, limited bandwidth, RC delay, and so on. On-chip interconnect implemented in the optical domain has been considered as a promising candidate toward next generation chip multiprocessor (CMP) with advanced performance.
In this study, we mainly focused on designing the communication system in short distance regime. First, we designed 3x3 and 4x4 non-blocking optical switches with high scalability, low propagation loss, and low power consumption. We analyzed the structure, signal quality, and compared with recent literatures. On basis of two frameworks, we applied them to different topologies such as ring and mesh for optical network on chip (ONoC) to achieve chip multiprocessor. Finally, we hope that the design strategies for optical switches and corresponded ONoC will provide a guideline for system level designer for choosing optimized topology in ONoC depending on implementation infrastructure.
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