Architectural Design and Analysis for Optical Network on Chip
碩士 === 國立清華大學 === 光電工程研究所 === 100 === As the transistors enters the scales of the nanometer regime, metallic interconnect will be highly inefficient in several issues, such as poor scalability, limited bandwidth, RC delay, and so on. On-chip interconnect implemented in the optical domain has been co...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91591509658191884692 |