| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 100 === This thesis presents the adder architecture for the flying-adder frequency synthesizer and the using the FPGA to complete the verification. The basic concept of this adder is to disrupt the cycle of the adder, thereby it reduces fractional spur. We also use the FPGA to implement the different types of flying-adder frequency synthesizer.
Flying-adder frequency synthesizer’s basic unit contains multiplexer, adder, digital-to-voltage converter, delay-locked loop, divider, digital interpolator and control unit. The SAR circuit uses to do lock algorithm, which is the binary search method, to achieve the purpose of fast locking. DLL output eight phases are interpolated with the digital interpolators. The DLL can output the 16 phases for the flying-adder. Multiphase digital Interpolator reduces the chip area.
The chip has been implemented in TSMC 0.18μm. The core area of the chip is 320.42×337.76μm2 and the total area is 937×937μm2. Flying-adder frequency synthesizer output frequency ranges from 60MHz ~ 110 MHz. The peak-to-peak jitter is 282.41ps and RMS jitter is 47.07ps when flying-adder frequency synthesizer’s output frequency is 62.28MHz.
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