The Implementation of Flying-Adder Based Frequency Synthesizer and Calibration Circuit
碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 100 === This thesis presents the adder architecture for the flying-adder frequency synthesizer and the using the FPGA to complete the verification. The basic concept of this adder is to disrupt the cycle of the adder, thereby it reduces fractional spur. We also u...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/79686277618978843230 |