Architecture and Implementation of LDPC Decoding Chip for DVB-T2
碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 100 === In this thesis, Sum-Product algorithm of decoder adopts Min-Sum algorithm. Traditional Min-Sum algorithm is full-parallel architecture, decoding requires two pieces of RAM to stores and updates calculation value which CNP and VNP calculate, and they can’...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/07018188595377136486 |