A Design Framework of Systolic Arrays for Tolerating Timing Errors

碩士 === 國立東華大學 === 電機工程學系 === 100 === Along with the progress of making semiconductor the technique of manufacturing integrated circuit skill take from 0.35um to 90nm and even smaller. Both power capacity and the mass of transistors reduction is what nowadays processor of semiconductor are after...

Full description

Bibliographic Details
Main Authors: Jiun-Nian Lai, 賴俊年
Other Authors: Hsin-Chou Chi
Format: Others
Published: 2012
Online Access:http://ndltd.ncl.edu.tw/handle/2p7hw3