Implementation of 10-bit 50MSPS Pipelined Analog-to-Digital Converter
碩士 === 國立東華大學 === 電機工程學系 === 100 === In this thesis, a 10-bit pipelined analog-to-digital converter (ADC) is implementation with TSMC 0.18um CMOS 1P6M mixed signal process. The sampling rate is 50MHz and the supply voltage is 1.8V. The overall circuit of architecture includes front-end sample an...
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| Format: | Others |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/vaqpaf |