Optimization of the Gate - Drain Capacitance to Improve the Switching Performance of Trench Power Metal-Oxide-Semiconductor Field-Effect Transistors

• Main Authors: Chen, Chi-Fu, 陳淇富
• Other Authors: Pan, Fu-Ming
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/59181487297802687295

碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 100 === Power MOSFETs are widely used as a switching device for high frequency and low voltage (<200 V) power converter. The switching rate depends on charging and discharging performance of the gate capacitor. Low gate - drain charge and low on-resistance can reduce switching power loss and thus improve the device performance. Many approaches have been developed to increase the unit cell density to reduce the on-resistance in trench type power MOSFETs, but the switching will become slower while the gate parasitic capacitance increases. This thesis presents the investigation on narrowing the trench width to reduce the gate - drain capacitance. For the sake of cost considerations, the i-line stepper was used for the wafer production process instead of deep-UV stepper, therefore the trench width was limited by the lithography resolution. After the first step of hard mask etching, a TEOS thin film was deposited on the edge of the hard mask region to form a sidewall spacer, which defined the second hard mask for bulk etching. The spacer could narrow the width of the etched trench to 0.15 ?慆. Combining precise control of ion implantation and furnace drive-in processes for the P-WELL region, optimization of the trench width and depth using the new hard mask approach can effective reduce the gate – drain capacitance, and thus the feedback capacitance of the MOSFET.