Design of 0.5-V Low-Jitter Phase-Injection Phase-Locked Loop
碩士 === 國立交通大學 === 電控工程研究所 === 100 === This thesis proposes two phase-injection phase-locked loops (PLLs), which focus on low-jitter and low-voltage design. The first version of PLL employs a multi-band voltage-controlled oscillator (VCO) with phase-injection. With the phase-injection mechanism, the...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60796666121564484940 |