A Study on Carbon Doping Technology and High-Performance Poly-Si Nanowire TFTs

• Main Authors: Lee, Chen-Ming, 李振銘
• Other Authors: Tsui, Bing-Yue
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/45850168179356052469

博士 === 國立交通大學 === 電子研究所 === 100 === In this dissertation, we studied the impact of the carbon (C) doping technology on the thermal stability of nickel monosilicide (NiSi) and the Ni-silicide-contacted n+/p junction. Moreover, using the low-temperature C ion implantation (I/I) technique followed by solid phase epitaxy (SPE) annealing, silicon-carbon (SiC) layer with high concentration of substitutional carbon could be achieved. Then, we successfully fabricated the high-performance poly-Si nanowire (NW) thin-film transistor (TFT) with a physical gate length (LG) of 30 nm. Good short-channel characteristics and high driving capability could be obtained by structural engineering. Furthermore, we discussed the influence of device geometry on the current transport mechanism. Two self-heating phenomena observed in poly-Si TFTs could be explained by different current transport mechanisms. Finally, we first observed the random telegraph noise (RTN) phenomenon in small-area poly-Si NW TFTs. The RTN phenomenon could also arise from the capture and emission of a carrier by the grain-boundary trap, which was confirmed by model derivation and high-temperature measurements. We adopted the plasma immersion ion implantation (PIII) technology to implant C ions into the Si substrate surface. PIII has the advantages of high ion fluences and low energy implantation. However, for low energy and long period PIII process, a diamond-like carbon (DLC) film simultaneously deposited on the Si substrate surface and prevented Ni-silicide formation. Therefore, the silicide formation temperature must be raised to 800 °C. Another I/I method used in this study is the conventional C I/I process. Implanting C ions into the Si substrate surface could improve the thermal stability of the NiSi film, especially for the agglomeration phenomenon at high temperatures. The efficiency of improvement is related to the amount of C atoms at the NiSi/Si interface. With sufficient C concentration, the agglomeration and phase transformation temperatures of the NiSi film could be raised to higher than 850 ?aC. Even if the Ni-silicide film was thin, the C doping technology could still effectively raise the agglomeration temperature of the Ni-silicide film at high as 300 ?aC. Moreover, For the Ni-silicide-contacted n+/p junction, after high-dose (5x1015 cm-2) C I/I and high-temperature annealing, there were still many residue defects existing in the Si substrate surface. During the formation of Ni silicide, a large number of Ni atoms would rapidly diffuse and arrive at the junction depletion region via these defects, which caused the increase of the n+/p junction leakage current. We have successfully fabricated the SiC film with substitutional C concentration of 1.046 % by optimizing the C I/I and SPE annealing processes. Nevertheless, excess C concentration retarded the SPE regrowth rate in the amorphous Si region. Therefore, the incomplete recrystallization and phosphorus (P) dopant redistribution phenomena were observed and both resulted in the increase in sheet resistance of the recrystallized SiC film. After the integration of the gate-all-around (GAA) structure, ultra-thin and narrow poly-Si body, and modified Schottky barrier (MSB) source/drain (S/D) junction, the high-performance poly-Si NW TFT with LG= 30 nm was successfully realized. It had good transfer characteristics. The fully-Ni-silicided S/D was agglomerated owing to the thinner NiSi film, which could be resolved by the C I/I technology. We also discussed the effects of the short channel, narrow width, and ammonia (NH3) plasma treatment on the dc characteristics of the poly-Si NW TFTs. When the silicon dioxide (SiO2) gate dielectric was further replaced by high permittivity (high-?? hafnium oxide (HfO2), the driving current of the high-performance poly-Si NW TFT biased at low gate and drain voltages (VGS= 2.587 V and VDS= 1 V) was up to 549 μA/μm. This value is the highest among the published literature. These experimental results open the possibility that poly-Si TFTs could be applied in three-dimensional integrated circuits (3D IC). We also found different current transport mechanisms in poly-Si TFTs. The current transport mechanism in large-area poly-Si TFTs is considered as thermionic emission. However, the current transport mechanism in small-area poly-Si TFTs transformed into the drift-diffusion model owing to the disappearance of the grain-boundary effect. Therefore, as the self-heating effect (SHE) occurs in poly-Si TFTs, the on-state current increases in large-area poly-Si TFTs but decreases in small-area poly-Si TFTs. Finally, we analyzed the RTN phenomenon in small-area poly-Si TFTs, such as time-domain and frequency-domain analysis. In addition to the gate oxide trap and the interface state, we also derived the carrier number fluctuation model induced by the grain-boundary trap. By high-temperature measurements, we proved that a capture and a release of a carrier by the grain-boundary trap could also cause the RTN phenomenon. As poly-Si TFTs are applied to future 3D IC or 3D nonvolatile memories, the RTN phenomenon induced by the grain-boundary trap should be considered.