| Summary: | 博士 === 國立交通大學 === 電子研究所 === 100 === This dissertation investigates and analyzes the drain current mismatch and low frequency noise properties for nanoscale MOSFETs. Through a comparison of the input-referred noise and the trap density of the gate dielectric/semiconductor interface between co-processed strained and unstrained pMOSFETs, it is found that the tunneling attenuation length λ for channel carriers penetrating into the gate dielectric is reduced by uniaxial strain. This reduced λ may result in smaller carrier-number-fluctuations origin low frequency noise, which represents an intrinsic advantage of low frequency noise performance stemming from process-induced strain. On the other hand, it is found that the normalized drain current noise of the strained device in the high gate overdrive (Vgst) regime is larger than its control counterpart. In addition, the enhanced carrier-mobility-fluctuations origin 1/f noise for the strained device in the high |Vgst| regime indicates that the carrier mobility in the strained device is more phonon-limited, which represents an intrinsic strain effect on the low frequency noise.
Impact of uniaxial strain on drain current mismatch and its temperature dependence under various operation conditions are investigated systematically. With the adoption of uniaxial compressive strained silicon, drain current mismatch for the strained device in the low |Vgst| regime is enhanced while the threshold voltage mismatch of the strained device is nearly identical to that of the control one. The increased drain current mismatch for the strained device can be attributed to the enhanced gm/Id. In the high |Vgst| linear region, the smaller drain current mismatch for the strained device results from its smaller current factor mismatch σ(Δβ)/β. In the high |Vgst| saturation regime, the improvement in drain current mismatch for the strained device is further enhanced because of the strain-reduced electric field for velocity saturation (Esat).
Regarding the temperature dependence of the device mismatching properties, our result indicates that the drain current mismatch versus temperature trend for the strained device is different from the unstrained one. In the high |Vgst| linear regime, the compressively-strained device shows smaller increment in drain current mismatch than the unstrained counterpart as temperature decreases. In the high |Vgst| saturation region, opposite to the unstrained case, the drain current mismatch of the compressively-strained device decreases with temperature. The underlying mechanism is the larger temperature sensitivity of carrier mobility for the strained device.
The mismatching properties in nanoscale MOSFETs with symmetric/asymmetric halo implant are also investigated. We show that the threshold voltage mismatch is mainly determined by the RDF in the halo-implanted region, and the threshold voltage mismatch for the asymmetric device is larger than that of the symmetric one.
Impact of self-heating on drain current mismatching properties for SOI devices are investigated. It is found that self-heating induces a feedback effect and reduces the drain current mismatch. A drain current mismatch model considering the self-heating induced feedback effect is proposed. The accuracy of the new model has been verified with experimental data. This effect needs to be considered when one-to-one comparisons between SOI and bulk devices regarding the variability are made. In addition, impact of source/drain series resistance on the drain current mismatch is investigated. The impact of source/drain series resistance on the drain current mismatch will become increasingly important for devices with scaled channel length.
Since subthreshold circuits are increasingly important for low power applications, subthreshold drain current mismatch modeling is crucial. To model the subthreshold drain current mismatch more physically and accurately, our study suggests the constant-current method instead of the maximum slope method should be used for the determination of threshold voltage. Our study indicates that the subthreshold swing mismatch is important for devices with small geometries. It is also found that the correlation between the threshold voltage mismatch and the subthreshold swing mismatch needs to be considered in the subthreshold drain current mismatch modeling especially for long channel devices.
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