A low power digitally controlled oscillator based on interlaced hysteresis delay cells
碩士 === 國立交通大學 === 電機學院電子與光電學程 === 100 === As technology advances, portable devices become more and more popular. In portable devices, the power consumption becomes an important design issue. An all digital phase lock loop (ADPLL) has been widely used in frequency synthesizer and communication system...
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| Format: | Others |
| Language: | en_US |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90348117689202908515 |
| Summary: | 碩士 === 國立交通大學 === 電機學院電子與光電學程 === 100 === As technology advances, portable devices become more and more popular. In portable devices, the power consumption becomes an important design issue. An all digital phase lock loop (ADPLL) has been widely used in frequency synthesizer and communication systems. Digitally controlled oscillator (DCO) is the key component of performance and power of ADPLLs. The operated range and delay resolution of the DCO dominate jitter and output range of an ADPLL. A DCO occupies over 50% power consumption of an ADPLL. Power reduction on a DCO can effectively cut down the overall ADPLL power.
This work proposes a novel delay cell in low power applications. The interlaced hysteresis delay cell has low power consumption, small area and high quality. The DCO structure uses the modified binary-weighted delay stage and cascade-stage structure. However, the disadvantages of the structure are the serious glitches and the limited fastest frequency. The proposed solution uses a synchronization cell to avoid glitches. Moreover, the proposed DCO also increases the fastest frequency. This chip is implemented with standard cell library by synthesis and auto place-and-route tools. The low power DCO is fabricated in 90nm 1P9M standard CMOS process. The proposed IHDC reduces over 87% power consumption on the standard DCO which is based on AND gates. The power consumption of the proposed DCO is 128uW at 480MHz.
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