On analyzing and Improving ESD protection in Area-I/O Flip-Chip Design

• Main Authors: Liang, Yi-Cheng, 梁以正
• Other Authors: Chen, Hung-Ming
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/51145955662457181637

碩士 === 國立交通大學 === 電機學院電子與光電學程 === 100 === Now the demands of electrical product are multi-function, lightweight and low profile. Based on this concept, the package methods have to meet high density trend. Flip-chip is a mature technology on high density microsystem design and packaging. This structure using vertical connection to substitute bonding wire can reduce the connection distance to get the benefits: high frequency demand, better noise control and less power consumption on metal. In general VSLI design, the circuit designers still use the I/O ring for chip design. The conventional I/O ring is the mature structure for ESD protection, but it increases the distance of connection. This trade-off loses the benefit from reducing the connection distance. In this study, we try to use the new I/O distribution structure by Area-I/O cell to keep the two benefits. In our analysis, this new method has a large improvement for ESD protection. And new algorithm of cell assignment on this structure can obtain better result than general assignment method. Finally, we consider the present VLSI design flow in this discussion. New method can be easily applied in the original working flow.