| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 100 === Traditionally, a bus interconnect is used as the interconnect in a multi-core system due to its low transmission delay. However, it can only serve one master core at a time, and thus becomes a bottleneck when the number of cores increases in the system. Therefore, Network-on-Chip (NoC) is proposed as the interconnect of a many-core platform. In a NoC-based many-core system, broadcast is costly, so we can’t apply the snoop-based cache coherence protocol to maintain the cache coherency. For this reason, a directory-based cache coherence protocol is commonly used for on-chip data coherency.
In this thesis, we use SystemC to implement an approximate-timed model of NoC, and realize the MESI directory-based cache coherence protocol. In addition, we develop a hybrid interconnect by clustering a small number of cores using bus to reduce the traffic in the NoC. We evaluate it by executing the SPLASH-2 Benchmarks. According to the experimental results, the hybrid internconet can reduce the traffic in the NoC by 53%, 45%, and 39% respectively with 8, 16, and 32 cores compared to the baseline without clustering.
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