Study and Implementation of a Novel Seven-Level Inverter with Voltage-Balancing Circuit
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === The thesis proposes a novel seven-level inverter with voltage-balancing circuit. The new topology produces a low total harmonic distortion rate to implement a multilevel output. Moreover, introducing interleaved control to the new voltage-balancing circuit ma...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34029042780470618689 |