| Summary: | 碩士 === 國立成功大學 === 電機工程學系專班 === 100 === With the rapid development of semiconductor technology, the semiconductor device continues to shrink down, and thus make the switching speed and performance of integrated circuits (IC) continue to be promoted. Bottlenecks encountered when miniature metal connection in order to solve the switching speed of integrated circuits (IC). Copper conducting wire interconnect technology will be booming development, and has become today's VLSI process, mainstream technology. However new products’ production will encounter more problems and challenges. The metal film step coverage capability and gap fill capability will induce some issues in metal interconnect of the BEoL(Back End of Line)copper processing. Tiny Cu voids in the metal film deposition, this will definitely impact the performance and life-time of the semiconductor devices. Make the chip yield un-expected.
This thesis focuses on how to improve the process defects (Cu void) encountered in BEoL copper processing? Thereby enhance the process yield for further study. Using 3W1H、third-order expansion methods for situation analysis, to find the problem occurred may be the reasons, and then various experiments to verify, confirm the problem main reasons. According to different reasons, to put various improvement methods, and then the process can meet optimization and standardization. After significantly reduced process defect (Cu void), thus yield can also be upgraded to the expected target.
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