Timing-Aware Clock Gating of Pulsed-Latch Circuits for Low Power Design
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === Low power design is a crucial issue in modern circuit design. Several techniques have been developed to save power consumption. Of those techniques, the pulsed-latch technologies replace flip-flops with pulsed latches due to smaller capacitance of the latter....
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78599450369133032917 |