Digital Circuit Design of Premise Part of Fuzzy Logic Controllers with Variable Circuit Structure
碩士 === 華梵大學 === 電子工程學系碩士班 === 100 === In this thesis, we proposed a variable circuit architecture for the premise part of a dual-input single-output fuzzy logic controller. The control circuit is designed in Verilog HDL, and a FPGA is used as the verification platform for the simulation and the veri...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47696744799754034011 |
| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 100 === In this thesis, we proposed a variable circuit architecture for the premise part of a dual-input single-output fuzzy logic controller. The control circuit is designed in Verilog HDL, and a FPGA is used as the verification platform for the simulation and the verification.
We use triangle fuzzy sets as the premise part circuit. The membership value and the slope of the fuzzy sets are calculated in real time to avoid taking large memory. The centers of the fuzzy sets for the premise parts can be adapted on-line without re-download.
To verify the reliability of the proposed fuzzy control circuit, a virtual inverted pendulum is written in MATLAB. We choose the self-construction learning algorithm to adjust the centers of the fuzzy sets for the premise parts and code in MATLAB to build a closed-loop adaptive fuzzy control system. We design a virtual fuzzy logic controller as the comparison. The simulation results are compared with the experimental results to verify the correctness of the proposed fuzzy controller and the reliability that the centers of the fuzzy sets for the premise parts can be adjusted on-line without re-download the chip, and according to the control objectives and output actions, select the appropriate operation circuit to achieve the feasibility of a variable circuit structure.
Keywords：Fuzzy logic controller、variable circuit architecture、Verilog HDL、FPGA
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