Digital Circuit Design of Premise Part of Fuzzy Logic Controllers with Variable Circuit Structure
碩士 === 華梵大學 === 電子工程學系碩士班 === 100 === In this thesis, we proposed a variable circuit architecture for the premise part of a dual-input single-output fuzzy logic controller. The control circuit is designed in Verilog HDL, and a FPGA is used as the verification platform for the simulation and the veri...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47696744799754034011 |