The Implementation of an Reed-Solomon Decoder with CPU Technology
碩士 === 大葉大學 === 電機工程學系 === 100 === The implementation of Reed Solomon decoding is realized by VHDL programming, which includes operations of CPU and RAM. The firmware program operated in CPU is with MIPS instruction formats, and stored in a block of RAM. MIPS instructions with the length of 32 bits...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05199808161887016088 |