The Design of High Speed Digital Frequency Synthesizer and All-Digital Phase-Locked Loop with an Adaptive Bandwidth
博士 === 元智大學 === 電機工程學系 === 99 === The design of high speed digital frequency synthesizer and all-digital phase-locked loop with an adaptive bandwidth are proposed in this thesis. First, for high speed digital frequency synthesizer, based on the modulo-N arithmetic, a new architecture of high-perform...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00765076114954284290 |